Home > Products > TriCore

Infineon TriCore

TriCore PDF Brochure

Licensable 32Bit Microcontroller Core

Infineon's TriCore™ is the first unified MCU-DSP architecture in a single core. Ideally suited to SoC applications that require both microcontroller and DSP functionality together with high performance, low cost and minimal power consumption, TriCore meets the needs of automotive, industrial, mass storage and communications applications where TriCore based ASSP silicon devices from Infineon are already successful. TC1MP-S is the synthesizable implementation of the TriCore architecture and is now available as an XPack from IPextreme. The XPack is a complete configurable subsystem (available in either VHDL or Verilog) with an industry standard AMBA AHB interface, enabling simple integration into the wider platform, saving engineering time and effort to market.

Open Licensing

The TC1MP-S Synthesizable core is just one of the cores available for license as part of Infineon's Open Licensing Program. This program allows the intellectual property to be licensed by anyone — system manufacturers, design houses, fabbed or fabless semiconductor companies - for inclusion in chip designs for manufacture at any foundry the licensee chooses.

Block Diagram

TriCore Units & Interfaces

Superscalar Four-Stage Pipelined CPU

  • 32-bit Load/Store Harvard Architecture
  • 3 pipelines: Arithmetic, Load-Store, & Loop
  • Single instruction Multiple Data capability

Control Features

  • Single-bit addressing and manipulation
  • Extract and insert data field instructions
  • Fast context switching (from 4 cycles)
  • 16 & 32-bit instructions, intermixable without boundary penalty

DSP Features

  • Dual 16-bit Multiplier Accumulators
  • Zero overhead loops
  • Addressing: Circular, bit-reverse, register indirect with post & pre-increment
  • Rounding, truncation, saturation, signed fraction support

Memory Protection

  • Native protection scheme
  • Optional MMU Coprocessor Interface
  • Up to 3 coprocessor available
  • Floating Point coprocessor available

Program Memory Interface (PMI)

  • 64-bit interface for up to 64KB of configurable, tightly coupled cache/scratchpad memory

Data Memory Interface (DMI)

  • 128-bit interface for up to 64KB of configurable, tightly coupled cache/scratchpad memory

Local Memory Bus (LMB)

  • 64-bit data, 32-bit address
  • Runs at CPU clock speed and supports 8, 16, 32 and 64-bit transfers
  • Support for dual external interfaces Flexible Peripheral Interface (FPI) Bus
  • 32-bit address and data de-multiplexed
  • Single and multiple transfers: 8, 16 and 32-bit

Interrupt Controller

  • Programmable: Up to 255 Interrupt priorities/sources

Debug Interface for Advanced Emulation

  • Access to internal registers and memory through JTAG port
  • Hardware, software and external breakpoints
  • Support for trace fuctionality

For more information about Tricore, please conatct us at info@ip-extreme.com.

For additional information from Infineon, please visit www.infineon.com.