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Freescale V1 ColdFire Processor Core Core Store

Freescale V1 ColdFire Brochure

The synthesizable 32-bit RISC V1 ColdFire Core is the smallest and lowest power processor in the ColdFire family. The V1 ColdFire’s small size and high 32-bit performance make it ideal for a wide variety of consumer, healthcare, and embedded systems applications. For DSP operations, the V1 ColdFire Core includes (optional) dedicated hardware multiplier-accumulator (MAC) and divider (DIV) units.

The V1 ColdFire Core supports up to 200 MHz of performance using a standard cell based design methodology in a generic 90-nm process technology. The V1 ColdFire CPU is based on a variable-length RISC architecture that allows instructions to be 16, 32, or 48 bits in length. The result is more efficiently packed code in memory, reducing memory requirements and lowering overall system cost.

All ColdFire cores (V1, V2, V3, and V4) share the same architecture and instruction set. Upward compatibility from V1 to V2, V3, and V4 ColdFire processors provides a smooth roadmap to higher performance designs. The Freescale Semiconductor 68K/ColdFire® architecture has been deployed in over half a billion production devices making it one of the most widely used embedded microprocessors in the world.

 

The instruction fetch and execution pipelines are decoupled by an instruction buffer. Instructions can be fetched in advance, thereby minimizing stalls and accelerating throughput.

FEATURES
  • 32-bit processor core with 24-bit address bus
  • AMBA 2 AHB unified instruction/data bus
  • Single-wire debug interface
  • Variable-length RISC architecture with 16, 32, and 48-bit instructions
  • Independent, decoupled instruction and execution pipelines
    • 2-stage Instruction Fetch Pipeline (IFP)
    • 2-stage Operand Execution Pipeline (OEP)
  • Static branch prediction to minimize change-of-flow execution time
  • Execute engines include ALU, barrel shifter, and optional MAC and DIV units
  • ColdFire Instruction Set Architecture Rev. C (ISA_C)
  • Standard ColdFire programming model with 16 general-purpose, 32-bit registers
  • Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
  • Optional debug support including trace and real-time debug (RTD) through a single-wire background debug module (BDM) interface
DEBUG SUPPORT

The optional debug unit provides a rich set of debug capabilities:

  • ColdFire Debug B+ functionality mapped into the single-pin BDM interface
  • 64x6-bit trace buffer provides programmable start/stop recording conditions plus support for continuous or PC-profiling modes
  • Capture of compressed processor status and debug data into trace buffer provides program trace capabilities
  • Compression of trace data enables capture of 500-1000 cycles of program trace in 64x6-bit trace buffer
  • Real time debug support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
  • Debug resources are accessible through the single-pin BDM interface or the privileged WDEBUG instruction from the core
  • Debug unit can use core clock (internally divided by 2) or a separate asynchronous clock
  • Separate clocks for processor and debug unit enable shutdown of debug unit when not in use
ECOSYSTEM

The entire ColdFire Family, including the V1 ColdFire Core, is supported by world-class development tools suites offered through leading tools developers including Freescale, Green Hills Software, Wind River Systems, Accelerated Technology/Mentor Graphics, and many others. Freescale’s CodeWarrior development tools offer a simple migration path from S08 to V1 ColdFire. Also supported are a rich set of real time operating systems, stacks, and drivers from Freescale partners. For more information, go to www.freescale.com.

GATE COUNT AND PERFORMANCE

Gate count and maximum frequency depend on synthesis tool and target technology. Example values for a typical 90-nm technology are:

  • 19K (NAND2 equivalent) gates for V1 ColdFire Core with optional MAC, DIV, and debug units excluded
  • 200 MHz
DELIVERABLES

The V1 ColdFire Core is delivered in Verilog source code and includes:

  • Synthesizable Verilog source code (Source version)
  • Encrypted synthesizable Verilog (Core Store version)
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for popular EDA tools
  • Complete documentation

The Source version of the V1 ColdFire Core is fully configurable (MAC, DIV, and debug units can be included/excluded through HDL parameter settings). The Encrypted version, available in the IPextreme Core Store, includes the MAC, DIV, and debug units and is non-configurable.

For more product information, please contact core.store@ip-extreme.com.